The present invention relates to computer systems and, more particularly, to a computer system with a processor that accesses memory via a system bus. A major objective of the invention is to reduce the time a write to an external memory excludes the use of a system bus for other operations.
Much of modern progress is associated with the proliferation of computers. While much attention is focussed on general-purpose computers, application-specific computers are even more prevalent. Such application-specific computers can be found in new device categories, such as video games, and in advanced versions of old device categories, such as televisions.
A typical computer includes a processor and main memory. The processor executes program instructions, many of which involve the processing of data. Instructions are read from main memory, and data is read from and written to main memory. Advancing technology has provided faster processors and faster memories. As fast as memories have become, they remain a computational bottleneck; processors often have to idle while requests are filled from main memory.
One approach to reducing this bottleneck is to use multiple memories. For example, a small-fast memory can be used with a larger slow main memory. This approach provides for a performance improvement to the extent operations can involve the smaller faster memory.
Caches are a specific class of small fast memories designed to reduce the bottlenecks imposed by accesses to main memory. Caches intercept requests to main memory and attempt to fulfill those requests using memory dedicated to the cache. To be effective, caches must be able to respond much faster than main memory; to achieve the required speed, caches tend to have far less capacity than main memory has. Due to their smaller capacity, caches can normally hold only a fraction of the data and instructions stored in main memory. An effective cache must employ a strategy that provides that the probability of a request for main-memory locations stored in the cache is much greater than the probability of a request for main-memory locations not stored in the cache.
Caches reduce the frequency of main-memory accesses for read operations, but not for write operations. If an address asserted in a read operation is represented in the cache, the copy of the data in the cache is transmitted to the processor in lieu of the data in main memory. Whether or not an address asserted in a write operation is represented in a cache, data must be written (sooner or later) to main memory. (The exceptions to these generalizations do not alter the essential distinctions between the read and write operations.) When a write operation involves writing to a cache, the cache effectively serves as a buffer in the transfer to main memory.
It is not necessary to limit the advantages obtained by buffering write operations to those write operations that assert addresses represented in a cache. Many systems now include write buffers that buffer every write operation. These write buffers can be integrated with a read/write cache or operate independently of a read cache. Every write operation can involve a write to the buffer. The buffer can then manage the transfer to main memory while the processor is freed to execute subsequent operations.
While the write buffer frees the processor from having to wait for data to be written to main memory, it does not significantly reduce the time that the system bus is occupied with write operations. The system bus can thus remain a bottleneck. Processing can be delayed while write operations are issued if the write buffer is full and cannot be freed because the system bus is occupied. Also, read operations involving addresses not represented in the read cache can be delayed. In addition, other types of transfers, e.g., with other processors or devices, involving the system bus, can be delayed while the system bus is occupied with these write operations. What is needed is a system that reduces the load imposed on the system bus by write operations.
The present invention provides a computer system with a system-bus buffer for buffering memory-access requests. The memory requests include write requests, but can also include read requests. Preferably, the system-bus buffer is a first-in-first-out (FIFO) device. Also preferably, the system-bus buffer stores, in addition to address and content data, control data such as transfer width and transfer type (e.g., sequential versus non-sequential).
A method of the invention provides for a processor issuing a write operation, a system bus transferring the write information, a system-bus buffer storing the write information, a memory bus transferring the write information, and memory storing the write data as requested. Preferably, the method includes the steps of a processor bus transferring the write information, and a processor write buffer storing the write information. These steps occurring in the written order after the processor issues the write operation and before the system bus transfers the write information.
For systems with plural memory controllers, the invention provides a shared system-bus buffer that also stores device-select information. In this vein, a system can have one controller for conventional RAM-based main memory and another controller for flash memory. The flash memory, or other programmable non-volatile memory, can be used to store and upgrade an operating system and/or application-specific programs.
The present invention provides for occupying the system bus only while a write operation is stored in the system-bus buffer, rather than until completion of a write operation. Thus, the system bus can be available for other operations while data is being written to memory. For example, a local fast memory can be accessed during a write to a slower external memory. (Of course, there will be exceptions, e.g., when the buffer is full and when operations contend for other common resources.)
The invention provides alternatives for handling read requests that are not fulfilled from cache. One approach is to buffer all missed read requests just as the write requests are. A second approach is to have read requests bypass the system-bus buffer; there is less to be gained by buffering a read request and bypassing the buffer can sometimes avoid a latency associated with the buffer. A third approach is to bypass the buffer when it is empty, but not otherwise. In this hybrid approach, the system bus is freed for other uses during a read operation unless a latency can be avoided by not buffering the read operation.
Placing two buffers (a processor write buffer and a system-bus buffer) in series along the write path from a processor to main memory would be expected to achieve some performance advantage associated with a greater total buffer capacity. However, such a gain can usually be obtained more efficiently by simply using a larger buffer. Surprisingly, the present invention provides, in many contexts, for performance gains that far exceed that achievable simply by expanding the capacity of the processor write buffer. The favored contexts include systems with multiple processors, systems with multiple memory controllers, and, more generally, systems with system buses involved in many different types of data transfers. These and other features and advantages of the invention are apparent from the description below with reference to the following drawings.